1. Field of the Invention
The present invention relates to a flash memory, and more particularly, to methods and systems of error correction code (ECC) for a flash memory.
2. Description of the Related Art
Due to increasing capacities, flash memories have become an alternative to the traditional motor-driven disks in many applications, such as portable devices. Since flash memories contain no mechanical parts, they exhibit advantages such as shock resistance, low power consumption and high speed compared to motor-driven disks. However, flash memories have their own limitations. One limitation is that each read/write unit of a flash memory should be erased before writing. Another limitation is that each read/write unit of a flash memory has a limited life of erase-write cycles, and exceeding the limited erase-write cycles may cause unpredictable defective bits spread throughout the flash memory.
Traditionally, a flash memory can utilize techniques such as the ECC, Wear-Leveling Algorithm (WLA) and Bad Block Management (BBM) to reduce the performance degradation caused by the above limitations and thus lengthen the lifetime of the flash memory. To utilize the ECC, WLA and BBM techniques, each flash page, which is the smallest read/write unit of a flash memory, should comprise a data area and a spare area, wherein the data area stores the user data and the spare area stores the management data including the information required by ECC, WLA and BBM techniques.
However, a flash memory can only erase one flash block at a time. Furthermore, a flash block usually contains 32 or more flash pages. Therefore, once the number of defective bits exceeds the correction capability of a flash page, the whole flash block is usually marked as a defective block by the BBM technique. If marked as a defective block, all the flash pages of the flash block will not be accessed for future read/write operations, which is a waste of memory space, since many flash pages in the same flash block are still within the capacities of the ECC technique and therefore usable.
U.S. Patent Application US2008/0168319 discloses a method and a system. As shown in FIG. 1, an ECC controller 100, encoding and decoding data transacted with a flash memory 1000, comprises an ECC encoder 102 and an ECC decoder 104. The ECC encoder 102 comprises a first encoder 106 and a second encoder 108. The ECC decoder 104 comprises a first decoder 110, a second decoder 114 and a decoding controller 112. The first encoder 106 and the first decoder 110 constitute a codec with high encoding/decoding speed but low ECC capacity, while the second encoder 108 and the second decoder 114 constitute a codec with low encoding/decoding speed but high ECC capacity. For each write datum, the first encoder 106 generates a first ECC datum, and the second encoder 108 generates a second ECC datum, while the length of the second ECC datum is longer than that of the first ECC datum. For each read datum, the first decoder 110 decodes a first ECC codeword, which is the combination of the first ECC datum and the read datum. If the errors of the decoded ECC codeword are beyond the ECC capacity of the first decoder 110, the second decoder 114 then decodes a second ECC codeword, which is the combination of the second ECC datum and the read datum. Consequently, a compromise between the processing speed and the ECC capacity is achieved.
The method and system in U.S. Patent Application US2008/0168319 is that each datum stored in the flash memory 1000 requires two storage spaces for the ECC data, which limits the available memory space. The ECC controller 100 comprises only two ECC codecs, and thus the ECC capacity thereof is fixed. The ECC controller 100 could comprise three or more ECC codecs to enhance the flexibility of the ECC capacity, but this would further limit the available memory space since each datum requires more storage spaces for the ECC data.
In view of the aforesaid conventional techniques, there is a need to design an apparatus and a method to lengthen the lifetime of a flash memory, while reducing the required memory space to far less than that of the conventional techniques.